VHDL Programming

Now we're going to study one of the most popular languages for hardware description. VHDL means Very High Speed Integrated Circuit Hardware Description Language it was founded by the American Department of defense in order to describe hardware.

Where VHDL is used?

Like Verilog VHDL is used to develop cores inside an FPGA, CPLD, or ASICs. It's used with a synthesizer tool that will convert the VHDL code to a gate-level netlist.

Difference of VHDL from other procedure languages

One big difference of VHDL from other languages is based on the fact that assignments can be executed in two forms:

Other important fact is that we can code our VHDL project in different levels of abstraction

Simple Flip-Flop D sample

Let's describe the same Flip-Flop D from Verilog tutorials and test it in our starter kit.

We're going to use the sabe constraint file from the other sample.

library IEEE;
   use IEEE.STD_LOGIC_1164.ALL;
   use IEEE.STD_LOGIC_ARITH.ALL;
   use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mod_ffd is
   Port ( RESET : in  STD_LOGIC;
   CLK : in  STD_LOGIC;
   Q : out  STD_LOGIC;
   NQ : out  STD_LOGIC;
   D : in  STD_LOGIC);
   end mod_ffd;
architecture Behavioral of mod_ffd is
begin
   -- FlipFlop D sample (By the way that's a comment)
   process(RESET, CLK, D)
   begin
   if RESET = '1' then
     Q <= '0';
     NQ <= '1';
   elsif rising_edge(CLK) then
     Q <= D;
     NQ <= not D;
   end if;
   end process;
end Behavioral;

Some interesting point to observe is that VHDL is case insensitive. Let's see the video of this module working in our board.

In this tutorial we're going to use Xilinx ISE tool, the video bellow will show how to create this project step by step.

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